Network interface unit including a microcontroller having multiple configurable logic blocks, with a test/program bus for performing a plurality of selected functions

Abstract

A network interface unit is presented including a microcontroller having multiple blocks of programmable logic that are variably configurable to perform selected functions. The network interface unit may be configured to assemble, transmit, and receive data units (i.e., frames) of one communication protocol, then later reconfigured to assemble, transmit, and receive frames of another protocol. The microcontroller includes several components formed upon a single monolithic semiconductor substrate, among them an execution unit. The execution unit includes a processor core and multiple configurable logic blocks (CLBs) coupled to the processor core. The processor core is configured to execute instructions, for example x86 instructions. Each of the multiple CLBs includes programmable logic which may be, for example, PLA circuitry, PAL circuitry, or FPGA circuitry. The programmable logic includes programmable switching elements such as, for example, EPROM elements, EEPROM elements, or SRAM elements. During instruction execution, the processor core produces output signals. During a programming operation, the output signals include programming signals which configure the programmable logic within one or more of the multiple CLBs to perform selected functions. Once programmed, each CLB performs the selected function in response to output signals produced by the processor core. The network interface unit also includes one or more memory devices and an electrical interface unit. The one or more memory devices store instructions and data used by the processor core. The electrical interface unit is adapted for coupling to the network transmission medium and performs as an interface between the microcontroller and the network transmission medium.