Clock recovery for multiple frequency input data

Abstract

Clock recovery circuits and methods include a first phase locked loop that generates a control signal in response to a reference clock. A pulse generating and delaying circuit is responsive to the input data signal to generate from the input data signal pulses of predetermined width that are delayed by a predetermined delay. A second phase locked loop is responsive to the control signal, to the pulse generating and delaying circuit and to a mode signal, to generate a clock signal from the input data signal. Accordingly, only the first phase locked loop need include a reference clock. Moreover, in an integrated circuit that includes multiple data ports, only the pulse generating and delaying circuit and the second phase locked loop may need to be duplicated for each data port, to allow each data port to operate at a frequency that is independent of the other data ports. A common first phase locked loop, including a common reference clock, may provide a common control signal to all data ports.