The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 22, 2001
Filed:
Feb. 22, 2000
Applicant:
Inventors:
Athanasia Chrysostomides, München, DE;
Robert Feurle, Neubiberg, DE;
Robert Kaiser, Kaufering, DE;
Helmut Schneider, München, DE;
Assignee:
Siemens Aktiengesellschaft, Munich, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 ;
U.S. Cl.
CPC ...
G11C 7/00 ;
Abstract
The integrated semiconductor memory configuration has a plurality of memory cell fields connected to one another by low-resistance supply lines forming a power network. The power network is connected to a voltage generator via a high-resistance supply line. An activated memory cell field is supplied, for the purpose of such activation, by self-buffering from the other memory cell fields (,).
Quick Actions:
Chrysostomides, Athanasia. (2001). Integrated semiconductor memory configuration with self-buffering of supply voltages (U.S. Patent No. 6236612). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6236612
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile