The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2001

Filed:

Jan. 26, 2000
Applicant:
Inventors:

Eugene A. Roylance, Boise, ID (US);

Robert D. Morrison, Star, ID (US);

Assignee:

Hewlett-Packard Company, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B41J 2/435 ;
U.S. Cl.
CPC ...
B41J 2/435 ;
Abstract

An embodiment of an edge placement device is supplied with transition data to generate transitions during a pixel time period corresponding to the transition data. The transition data is supplied by pulse code logic that converts pixel data to the transition data. The embodiment of an edge placement device includes first edge placement logic coupled to taps from a first clock delay chain and second edge placement logic coupled to taps of a second clock phase delay chain. Also included is a phase splitter that generate a first and a second clock phase coupled, respectively, to the first and the second clock delay chain from a clock corresponding to a pixel time period. The first and the second clock phase have rising edges on alternate cycles of the clock. The first and the second edge placement logic each include a plurality of D flip flops. The clock inputs of each of the flip flops in the first and the second edge placement logic are coupled, respectively, to one tap from first or the second clock delay chain. The D inputs of the flip flops of the first and the second placement edge placement logic are coupled, respectively, to a first and a second data phase provided by the pulse code logic. By setting the values of the first and the second data phases, supplied on alternate cycles of the clock, video data is generated having transitions during the pixel time period corresponding to the pixel data.


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