The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2001

Filed:

Nov. 22, 1999
Applicant:
Inventors:

Kenichiro Choumei, Tokyo, JP;

Kazutomi Mori, Tokyo, JP;

Akira Inoue, Tokyo, JP;

Toshio Okuda, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03G 5/16 ; H03F 3/04 ;
U.S. Cl.
CPC ...
H03G 5/16 ; H03F 3/04 ;
Abstract

A bias circuit and bias supply method for a multistage power amplifier including heterojunction bipolar transistors for power amplifying a high frequency signal and suppressing an increase in Rx noise during low power output operation of the multistage power amplifier. The bias circuit outputs a control signal Vapc from an external control circuit to the base of only a first-stage amplifier HBT in the multistage power amplifier. To the base of the second and each later power amplifying stage HBT of the multistage power amplifier, the bias circuit supplies a bias current regulated by voltage stabilizers according to the control signal Vapc.


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Choumei, Kenichiro. (2001). Bias circuit and bias supply method for a multistage power amplifier (U.S. Patent No. 6236266). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6236266

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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