Active undershoot hardened fet switch

Abstract

A bus switch for transferring logic signals between nodes without the problems associated with undershoot conduction. The bus switch is an FET switch including a single primary transfer transistor. The bulk of the transfer transistor is coupled to a differential logic sense circuit that is designed to establish a pseudo low-potential power rail. The logic sense circuit is coupled to the two transfer nodes and a standard low-potential power rail. It compares the potentials associated with the transfer node signals and the low-potential rail and selects the one with the lowest potential to establish the potential of the pseudo low-potential rail. The logic sense circuit provides for active selection of the lowest potential element, including under very small undershoot conditions. The logic sense circuit may be established in a variety of ways, preferably by including a differential comparator pair, one of associated with one of the two transfer nodes and the other differential comparator associated with the other transfer node. Outputs of the differential pair control logic drivers that in turn regulate the transfer node, or standard low-potential rail to be coupled to the pseudo low-potential power rail. This arrangement ensures that there will be no parasitic conduction of the transfer transistor during undershoot conditions.