Power-on reset circuit for a high density integrated circuit

Abstract

A power-on reset circuit reduces power consumption and layout area by utilizing a time delay to deactivate a reset circuit and clamp a reset signal a period of time after a power supply voltage has reached a predetermined level. The reset circuit includes a reset signal generator which maintains the reset signal in an active state until the power supply voltage has reached the predetermined level. The reset signal generator then deactivates the reset signal which causes a delay circuit to begin a time delay after which a delay signal is asserted. The delay signal deactivates a comparator in the reference voltage generator, a voltage detector, and a reset signal generator within the reset circuit, thereby reducing power consumption. The delay signal also activates a clamp circuit which clamps the reset signal to an inactive state.