The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2001

Filed:

Oct. 22, 1999
Applicant:
Inventor:

Hiroki Koga, Kangawa, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03B 1/00 ; H03K 3/00 ;
U.S. Cl.
CPC ...
H03B 1/00 ; H03K 3/00 ;
Abstract

An output buffer circuit is provided, which decreases a delay time of change of a digital output signal with respect to change of a digital input signal and which is capable of higher-speed switching operation. This output buffer circuit is comprised of a pair of a first p-channel MOSFET and a first n-channel MOSFET located in an output stage through which an output signal is derived; a first clamp circuit for clamping a gate voltage of the first p-channel MOSFET at a first clamp level for a first specific period, thereby increasing a rising rate of the output signal; and a second clamp circuit for clamping a gate voltage of the first n-channel MOSFET at a second clamp level for a second specific period, thereby increasing a falling rate of the output signal. A first resistor is connected to the first clamp circuit for suppressing a current flowing through the first clamp circuit. A second resistor is connected to the second clamp circuit for suppressing a current flowing through the second clamp circuit. A first capacitor is connected to the first clamp circuit for adjusting the gate voltage of the first p-channel MOSFET through its charging or discharging operation. A second capacitor is connected to the second clamp circuit for adjusting the gate voltage of the first n-channel MOSFET through its charging or discharging operation.


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