Method and system for translating ttl off-chip drive for integrated circuit with negative substrate bias

Abstract

The present invention provides a method and system for translating a signal from a chip with a negative substrate bias. The method and system includes receiving an input signal in a first state in a first logic level, the first state being approximately at ground; and translating the input signal to a second state in a second logic level, the second state being above ground. The method and system translates a signal from a chip with a negative substrate bias. In the preferred embodiment, the method and system of the present invention uses a translation circuit to translate and drive the signal off-chip. The translation circuit in accordance with the present invention functions with a positive Vcc and a Vee lower than ground, and also does not violate any of the rules of functionality for components used in a chip which has a negatively biased substrate and a voltage limit on its components. The method and system allows the translated signal to be driven off-chip and be compatible with standard TTL logic levels. A pre-amp chip which uses the translation circuit of the present invention is able to maintain a fast data rate and to take advantage of the low cost of the silicon process used for the chip.