The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 22, 2001
Filed:
May. 28, 1999
Jeffrey Mark Marshall, Austin, TX (US);
Cypress Semiconductor Corp., San Jose, CA (US);
Abstract
A product-term allocation architecture for a programmable device, comprising a plurality of logic gate sections and a fully rotatable, programmable OR-type array. A first one of the logic gate sections may comprise a first plurality of fixed logic gates. Each of the first plurality of fixed logic gates may have m inputs, m being an integer of at least one. A second one of the logic gate sections may comprise a second plurality of fixed logic gates. Each of the second plurality of fixed logic gates having n inputs, n being an integer of at least two and being different from m. The plurality of logic gate sections may be configured to provide p outputs, p being an integer equal to or greater than the total number of the fixed logic gates and less than the total number of fixed logic gate inputs. The fully rotatable, programmable OR-type array may receive the p outputs and may be configured to generate a plurality of array outputs.