Methods of forming integrated circuit contact holes using blocking layer patterns

Abstract

Integrated circuit contact holes may be formed on an integrated circuit substrate, by providing a first conductive pattern on the substrate, a first interlayer insulating film on the first conductive pattern, a second conductive pattern on the first interlayer insulating film and a second interlayer insulating film on the second conductive pattern. A blocking layer pattern is formed on the second interlayer insulating film. The blocking layer pattern overlies, is of the same pattern as, and is as least as wide as the second conductive pattern. The first and second interlayer insulating films are then selectively etched relative to the blocking layer pattern and the second conductive pattern, to form contact holes that expose the first conductive pattern. A photoresist pattern may also be formed on a portion of the blocking layer pattern. Then, the first and second interlayer insulating films are selectively etched relative to the photoresist pattern, the blocking layer pattern and the second conductive pattern, to form contact holes that expose the first conductive pattern. The above-described integrated circuit contact hole forming methods may also be used to form integrated circuit contact holes for integrated circuit memory devices. For integrated circuit memory devices, the first conductive pattern may correspond to pad electrodes, the second conductive pattern may correspond to bit lines, and capacitor contact plugs may be formed in the contact holes.