The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2001

Filed:

May. 06, 1999
Applicant:
Inventors:

Sung Chul Lee, Chungcheongbuk-do, KR;

Jae Seung Choi, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/18247 ;
U.S. Cl.
CPC ...
H01L 2/18247 ;
Abstract

Methods for fabricating a flash memory device which improves both charge retaining characteristics and characteristics of a gate insulating film are disclosed. The methods include the steps of respectively forming a tunneling oxide film and a peripheral oxide film on a cell and peripheral areas of a semiconductor substrate; forming a floating gate line on the tunneling oxide film; forming a first insulating film on a surface of the floating gate line; forming a second insulating film on an entire surface of the semiconductor substrate; forming a third insulating film on the second insulating film so that the third insulating film is thicker than the peripheral oxide film; removing the third insulating film and the second insulating film from the peripheral area by wet etching processes; removing the peripheral oxide film by a wet etching process; forming a gate insulating film on the surface of the semiconductor substrate in the peripheral area; depositing a conductive layer on the entire surface of the semiconductor substrate; selectively removing portions of the conductive layer, the third insulating film, the second insulating film, the first insulating film, and the floating gate line to form a control gate and a floating gate in the cell area, and a gate electrode of a thin film transistor in the peripheral area; and forming source/drain impurity areas within the surface of the semiconductor substrate at both sides of the control gate and floating gate and at both sides of the gate electrode.


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