Automatic generation of evaluation order for a function block diagram and detection of any associated errors

Abstract

The programming of programmable controllers and other sequential computing devices is facilitated by automatically generating an order for evaluating function blocks in a function block diagram and by automatically detecting any errors in a function block diagram which would adversely affect the generation of a unique evaluation order, such as illegal cycles, disconnected subnetworks, and/or wired-OR connections. The nodes affected by the noted errors are graphically displayed to the user, who then may use a graphical interface to edit the network until all the noted errors have been corrected. A recursive procedure analogous to a topological sort may be used to automatically generate a unique evaluation order. The blocks upstream from each “maximal” output are visited recursively from the input of one block to the output of a preceding block until a “minimal” node is reached which either is not preceded by other blocks or is preceded only by blocks which have already been visited, whereupon the current block is assigned the next available sequence number and the same procedure is used to process any nodes that are upstream from the next downstream output.