Mapping shared dram address bits by accessing data memory in page mode cache status memory in word mode

Abstract

A memory system includes a data memory for storing data and applications software and a distinct cache status memory for storing status information regarding the data memory. A memory controller generates timing and control signals for accessing the data memory in a page mode while concurrently accessing the cache status memory in a word mode. In the preferred embodiment, the data memory is accessed in a four word per page mode so that the memory capacity of the associated cache status memory can be up to seventy five percent smaller than the data memory. In order to conserve pins on the memory controller, the cache status memory shares a substantial portion of the address lines which are received by the data memory. Supplemental cache status address lines are generated by programmable control logic, which may be incorporated into the memory controller. Programmable control logic generates supplemental address lines based on the maximum number of data memory modules, the size of the largest on data memory modules and the number of cache status columns so that any of a variety of data memory and cache status memory configurations may be employed.