Apparatus and method for monitoring the performance of a microprocessor

Abstract

An apparatus and method are presented for monitoring the performance of a microprocessor. The apparatus includes performance monitoring hardware incorporated within the microprocessor. The performance monitoring hardware includes a memory unit for storing performance data. The memory unit includes multiple memory locations, each memory location being accessed by a unique set of address signals. Circuitry within the performance monitoring hardware produces the address signals. In one embodiment, the performance monitoring hardware includes an event select register array and circuitry for producing a set of high order (i.e., most significant) address signals. The event select register array preferably includes several event select registers for storing binary codes corresponding to selected events. A performance data acquisition period is divided into multiple histogram time periods of equal length. The high order address signals partition the memory unit into sections. Each section is associated with a given histogram time period and contains at least n memory locations, where n is the number of event select registers and the maximum number of selected events. Each section of the memory unit is used to store performance data relating to the selected events which occur during the corresponding histogram time period. Each occurrence of one of the n selected events during a given histogram time period results in the incrementing of the contents of a corresponding memory location within the corresponding section of the memory unit.