The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 15, 2001
Filed:
Jun. 22, 2000
Applicant:
Inventors:
Farshid Shokouhi, San Jose, CA (US);
Michael G. Ahrens, Sunnyvale, CA (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 1/600 ;
U.S. Cl.
CPC ...
G11C 1/600 ;
Abstract
A floating gate memory device that includes a column latch circuit that is isolated from a series of bitlines by PMOS pass transistors controlled by a bitline latch switch circuit. The bitline latch switch circuit selectively applies either +5 V or −2 V signals to the gate terminals of the PMOS pass transistors, thereby allowing the PMOS pass transistors to selectively pass 0 (zero) Volts during, for example, program operations. A −2 V charge pump is activated to generate the −2 V signal during operations requiring 0 Volt bitline voltages, and is turned off during all other operations.