Non-volatile semiconductor memory capable of reducing parasitic current

Abstract

A non-volatile semiconductor memory decreases a parasitic current as much as possible without using an electric separation means. This nonvolatile semiconductor storage apparatus has multiple memory cells rows having multiple memory cell transistors M,M,. . . whose gates are connected to word lines WL,, WL,. . . , respectively, and whose sources and drains are serially connected. This non-volatile semiconductor storage apparatus also has multiple column lines SBL,SVL,SVL,SBL,. . . which connect the connection nodes between the sources and drains of the memory cell transistors M,M,. . . in the column direction, a power source line PV,which supplies a prescribed electric potential to these column lines, first and second sense amplifiers which detect the electric potential level of the column lines or a current that flows through the column lines, sense column line selection means SS,SS,SS,SS,and,which connect column lines SBL,and SBL,connected to one terminal of selected memory cell M,and one terminal of selected memory cell M,respectively, to the first and second sense amplifiers A,and A,respectively. In this case, the memory cell M,is separated from the memory cell M,by a prescribed number of memory cells on the same memory cell row. This nonvolatile semiconductor storage apparatus further has power source supply column line selection means DS,DS,DS,DS,. . . which connect the column lines connected to the other terminals of the two selected memory cells to the power source line.