The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 15, 2001
Filed:
Nov. 10, 1999
Applicant:
Inventor:
Stuart W. Pullen, Raleigh, NC (US);
Assignee:
Intersil Corporation, Palm Bay, FL (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03F 3/38 ;
U.S. Cl.
CPC ...
H03F 3/38 ;
Abstract
The low jitter dead time circuit which uses one RC combination to set the turn on delay for both the upper and lower MOSFETs in the half bridge. This circuit minimized jitters in the turn on delay and results in matched turn on delays for both MOSFETs in a half bridge. This minimizes noise and distortion. This circuit is further designed to be used in conjunction with shunt regulators to reject ripple from the power supplies.