Pulse generating circuit

Abstract

There is disclosed a pulse generating circuit which comprises an oscillator circuit,receiving an input clock signal, a P-channel MOS transistor,having a gate connected to an output of the oscillator circuit,, a delay circuit,having an input connected to an output line,, an oscillator circuit,having an input connected to an output of the delay circuit,, an N-channel MOS transistor,having a gate connected to an output of the oscillator circuit,, an inverter,having an input connected to the output of the oscillator circuit,, a delay circuit,having an input connected to the output line,, an AND circuit,receiving an output of the inverter,and an output of the delay circuit,, and an N-channel MOS transistor,having a gate connected to an output of the AND circuit. In the case that the output line,is at a high level in an initial condition, if the input clock signal changes from a low level to a high level, the output of the delay circuit,having the input connected to the output line,becomes the high level, and the output of the inverter,becomes the high level, so that the AND circuit,turns on the N-channel MOS transistor,, with the result that the output line,is brought to the low level. Accordingly, if the input clock signal changes from the low level to the high level in a next cycle, the pulse generating circuit brings the output line to the high level, so that a normal pulse generating operation starts.