Integrated circuit devices having data buffer control circuitry therein that accounts for clock irregularities

Abstract

Integrated circuit devices include a data buffer that is responsive to a control signal, enabled to pass data received at a data input thereof to a data output thereof when the control signal is in an active logic state and disabled to block passage of data from the data input to the data output when the control signal is in an inactive logic state. A data buffer control circuit is also provided. The data buffer control circuit latches a latency signal in response to a control clock, generates the control signal from the latched latency signal and comprises a pulse generator that drives the control signal to its inactive logic state in-sync with an edge of the latency signal. This inactive control signal can be used to disable the data buffer.