The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 15, 2001
Filed:
Sep. 28, 1999
Kiichi Kikuchi, Maebashi, JP;
Yuji Ebinuma, Misato-Machi, JP;
Yasuo Hosaka, Maebashi, JP;
Yoshiyuki Wasada, Tamamura-machi, JP;
Kenji Kaneta, Tomioka, JP;
Hajime Hasegawa, Tamamura-machi, JP;
Mitsuaki Ootani, Maebashi, JP;
Taiyo Yuden Co., Ltd., Tokyo, JP;
Abstract
A hybrid integrated circuit device is provided which suppresses lowering of the inductance value of a mounted coil component. A hybrid integrated circuit device according to the present invention has such a structure that a wiring pattern is provided on at least one main face of a substrate, a laid core type coil component is mounted on at least one main surface of the substrate, and a conductor pattern including a ground pattern is provided at least either on a main face opposite to the surface of the substrate upon which the laid core type coil component is mounted or in an interior of the substrate. In particular, the hybrid integrated circuit device has a configuration such that a magnetic flux passing window, having an absence of ground pattern, is provided in an orthographic projection area corresponding to a winding portion of the coil component in the conductor pattern.