Thin film transistor and a fabricating method thereof

Abstract

The present invention relates to a thin film transistor and a fabricating method thereof wherein a source/drain region and a gate electrode are formed in the same layer, which improves the degree of planarization. Because source/drain electrodes and a gate electrode are formed by patterning the same layer with a single mask, the invention reduces the number of fabrication steps. The TFT includes an insulated substrate which is transparent, a source electrode and a drain electrode on the insulated substrate. The source and drain electrodes are separated from each other, and a gate electrode is between the source and drain electrodes on the insulated substrate. A gate insulating layer covers the source and drain electrodes and the gate electrodes on the gate insulating layer. An active layer is then formed on the gate insulating layer. Source and drain regions are formed at each end of the active layer corresponding to the gate electrode and a channel region is formed between the source and drain regions. A passivation layer is then formed on the gate insulating layer, wherein the passivation layer covers the active layer, first and second contact holes exposing the source and drain regions and the source and drain electrodes, respectively. A first wire formed on a predetermined part of the passivation layer electrically connects the source region to the source electrode through the first contact hole. A second wire formed on another predetermined part of the passivation layer electrically connects the drain region to the drain electrode through the second contact hole.