The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 2001
Filed:
Mar. 02, 1999
John A. Langan, Austin, TX (US);
Bruce L. Morton, Austin, TX (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A method and apparatus for performing mis-aligned read and write operations to a stack involves providing a memory array (,). The memory array is split into a high byte memory array (,) and a low byte memory array (,). Each memory array (,and,) has its own bus interface unit (,and,) respectively. The high byte bus interface unit (,) increments the address bits to the high byte memory array (,) on every access to compensate for mis-aligned data. However, the low byte bus interface unit (,) does not increment the address value before accessing the memory array (,). By doing so, memory is read from the memory arrays (,and,) in either 8 bit sizes or 16 bit sizes regardless of whether the stack structure implemented in memory array (,and/or,) contains aligned data or mis-aligned data.