Content addressable memory system with cascaded memories and self timed signals

Abstract

A system includes a plurality of content addressable memory (CAM) chips which are cascaded and connected to a common bus. Each of the CAM chips provides search results (hit, match address and multiple match). A hit signal and a multiple match signal are propagated from chip to chip. A system hit result is given from the furthest down stream CAM chip. The match address result of the system is given from the common bus, where on-chip self-timed signals guarantee that there is no driving contention on the bus. An example of the CAM chip includes an extra row including a model match line and modified core cells to provide a model miss signal. The self-timed signal is provided in response to the model match line. In another example of the CAM chip, each word is divided into two halves. The match lines of the two halves of the word are coupled by a NAND circuit, the output of which is coupled to an encoder of the chip. The CAM chip includes an extra row including a chain of model match lines. Two adjacent model match lines are coupled by a NAND circuit, the output of which provides the model hit signal. The self-timed signal is provided in response to the model hit signal.