The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 2001
Filed:
Jan. 28, 1999
Peter Chambers, Phoenix, AZ (US);
Subramanian S. Meiyappan, Tempe, AZ (US);
Swaroop Adusumilli, Tempe, AZ (US);
VLSI Technology, Inc., San Jose, CA (US);
Abstract
A system and method for using single address cycles and eliminating dual address cycles to transmit a target address in a computer system. The computer system comprises a bus, a central processing unit coupled to the bus, an initiator device coupled to the bus, and a target device coupled to the bus. The target device comprises a first configuration register which is adapted to use a configuration bit to indicate an address range of the target device. The central processing unit interrogates the first configuration register and communicates the address range indicated by the configuration bit to the initiator device. The initiator device comprises a second configuration register which is adapted to use a configuration bit to register the address range of the target device. The initiator device is adapted to disable its dual address cycle capability and transmit to the target device the target address in a single address cycle provided that the address range of the target device as indicated by the respective configuration bits in the first and second configuration registers is not less than a size of the target address.