Memory device using one common bus line between address buffer and row predecoder

Abstract

Disclosed is a semiconductor memory device to reduce the number of address bus lines. The semiconductor memory device according to the present invention includes a common data bus line, a plurality of address buffers coupled to the common data bus line for buffering external address signals, a refresh counter coupled to the common data bus line, including a buffer for providing refresh address signals, a first controller for selectively transferring the external address signals buffered in the address buffers to the common data bus line, and a second controller for selectively transferring the refresh address signals from the refresh counter to the common data bus line.