The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 2001
Filed:
Mar. 20, 2000
Kazuo Watanabe, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A nonvolatile semiconductor storage device is disclosed that can have memory cells with a narrower erase threshold voltage distribution, a low power supply voltage, and high access speeds. According to one embodiment, a nonvolatile semiconductor device (,) may include a detect mode that can determine if a selected memory cell (,-,to,-,) has an erase threshold voltage below a predetermined value. In a detect mode, a cell check signal CELLCHK is active, resulting in a cell check voltage generator circuit (,) generating a detect bias voltage. According to power switch control signals PSCTRL, a power source switch,connects the sources and well(s) of the memory cells (,-,to,-,) to the cell check voltage generator circuit (,). Word lines (,-,to,-n) of deselected memory cells are driven to a low power supply voltage. The word line deselect bias voltage and detect bias voltage can prevent low erase threshold voltage memory cells from generating leakage current on a bit line. In this way, it can be determined if a selected memory cell (,-,to,-,) has a low erase threshold voltage or not. The threshold voltage of low erase threshold voltage memory cells may then be raised with a write operation, which can create narrower erase threshold voltage distributions.