The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 2001

Filed:

Oct. 30, 1998
Applicant:
Inventors:

Duane Patrick Fridley, Indianapolis, IN (US);

Curtis L. Coffee, Indianapolis, IN (US);

Kevin J. Shelow, Indianapolis, IN (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04M 1/104 ;
U.S. Cl.
CPC ...
H04M 1/104 ;
Abstract

The present invention involves a module on a single board for a power line control system including a transmitter circuit, a receiver circuit, and a control circuit. The transmitter circuit sends signals over the power line. The receiver circuit receives signals sent over the power line. The control circuit couples to the transmitter circuitry and the receiver circuitry. The control circuit includes a microprocessor and associated memory. The memory includes instructions enabling the microprocessor to interpret the received signals, generate transmit signals, and control the circuit which controls the electrical appliance. The receiver circuit includes feedback for attenuating the input signal to the receiver circuit. The microprocessor includes an output signal for attenuating the input signal to the receiver circuit. The memory includes programmable memory which can be FLASH memory. The memory also includes serial EEPROM. The control circuit includes a low voltage reset for automatically resetting the microprocessor after a low voltage condition. The transmitter circuit provides a 6 volts peak to peak signal on a 5 ohm reactance loaded power line. The receiver circuit provides a minimum sensitivity of 25 mv over a loaded power line. The memory includes instructions for sending an automatic acknowledge upon receiving a valid signal. The instructions also include instructions for determining a start code by comparing bit count values for four consecutive bits.


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