The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 2001
Filed:
Nov. 12, 1999
Stuart W. Pullen, Raleigh, NC (US);
Harold A. Witlinger, Pennington, NJ (US);
Intersil Corporation, Palm Bay, FL (US);
Abstract
The OCL,receives two logic signals: the first, OC upper FET, is high when an over current condition exists in the upper FET,; the second, OC lower FET, is high when an over current condition exists in the lower FET,. When the over current condition is in FET,, PMOS,turns on and injects current into the summing junction of the integrator,through Rcl. The net effect is turn off the upper FET,and turn on the lower FET,. This reduces the current in FET,. As far as amplifier,is concerned, the net effect is gain compression. Since upper FET,is on less and the lower FET,is on more, the gain of the audio signal is reduced. When the over current condition is in FET,, NMOS,turns on and pulls current out of the summing junction, turns the lower FET,off, and turns the upper FET,on. The net effect is to reduce the current in the lower FET. At audio frequencies, the gain is reduced.