The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 2001
Filed:
Nov. 19, 1999
Benjamin William Mashak, Rochester, MN (US);
Robert Russell Williams, Rochester, MN (US);
Steven Howard Voldman, South Burlington, VT (US);
David TinSun Hui, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An active clamp circuit for digital circuits includes a first MOSFET serially connected between an upper power supply voltage and an input terminal to be clamped, and a second MOSFET serially connected between a lower voltage power supply and the input terminal. The voltages at the gates of the first and second MOSFETs are held at constant first and second reference voltages by a reference circuit and the first reference voltage at the gate of the first MOSFET is less than the second reference voltage at the gate of the second MOSFET. The first and second reference voltages can be changed by connecting the reference circuit to power supply voltages other than the power supply voltages to which the first and second MOSFETs are connected. The reference voltages can also be varied by adding stages of transistors which act as resistors in parallel to the reference circuit. When the first reference voltage is to be varied, it is recommended that the transistors of opposite type be biased independently. The clamping action can be switched on or off, and when the clamping action is switched off, the voltage on the first and second MOSFETs is kept from floating by connecting the gates to turn-off transistors. The device is particularly suited for use with silicon-on-insulator.