The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 2001
Filed:
Sep. 07, 1999
Sa-Nguan Boochakorn, Bangkok, TH;
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A mechanism for positioning and coupling an integrated circuit package to a system for testing the integrated circuit package with minimized solder flaking. A contactor floor holds the integrated circuit package for moving the integrated circuit package within the system for testing the integrated circuit package. A respective contactor pin couples a corresponding lead of the integrated circuit package to the system for testing the integrated circuit package when the contactor floor moves the integrated circuit package to a testing position. The respective contactor pin further includes a positioning protrusion that protrudes toward a side wall of the contactor floor and that slides along the side wall of the contactor floor when the contactor floor is moving the integrated circuit package toward and away from the testing position with respect to the respective contactor pin. In addition, the respective contactor pin includes a contacting protrusion that is disposed above the positioning protrusion on the respective contactor pin and that protrudes toward the side wall of the contactor floor. An axis of the respective contactor pin is bent away from the side wall of the contactor floor at an angle such that the contacting protrusion is separated from the corresponding lead of the integrated circuit package with at least a predetermined avoidance distance when the contactor floor is moving the integrated circuit package toward and away from the testing position with respect to the respective contactor pin. With such a separation, the contactor pin does not scrape along the corresponding lead of the IC package to result in minimization of solder flaking.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile