The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 2001
Filed:
Apr. 25, 2000
Richard Redl, Farvagny-le-Petit, CH;
Brian P. Erisman, San Francisco, CA (US);
Jonathan M. Audy, San Jose, CA (US);
Gabor Reizik, Pleasanton, CA (US);
Analog Devices, Inc., Norwood, MA (US);
Abstract
A method and circuit enable a voltage regulator to employ the smallest possible output capacitor that allows the regulator's output voltage to be maintained within specified boundaries for large bidirectional step changes in load current. This is achieved with a technique referred to as “optimal voltage positioning”, which keeps the output voltage within the specified boundaries while employing an output capacitor which has a combination of the largest possible equivalent series resistance (ESR) and lowest possible capacitance that ensures that the peak voltage deviation for a step change in load current is no greater than the maximum allowed. The invention can be used with regulators subject to design requirements that specify a minimum time T,between load transients, and with those for which no T,is specified. When no T,is specified, optimal voltage positioning is achieved by compensating the regulator to ensure a response that is flat after the occurrence of the peak deviation, which enables the output voltage to remain within specified limits regardless of how quickly load transients occur. Another embodiment enables the power consumption of the device being powered by the regulator to be reduced under certain circumstances, while still employing the smallest possible output capacitor that allows the regulator's output voltage to be maintained within specified boundaries. The invention is applicable to both switching and linear voltage regulators.