The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 2001

Filed:

Sep. 29, 1999
Applicant:
Inventors:

Luis J. Garces, Schenectady, NY (US);

Timothy M. Rowan, Wauwatosa, WI (US);

Assignee:

Rockwell Technologies, LLC, Thousand Oaks, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02P 5/34 ;
U.S. Cl.
CPC ...
H02P 5/34 ;
Abstract

A method and apparatus for maintaining both a DC bus voltage and a motor current within limit values wherein, when a voltage limit condition occurs, a voltage error (i.e. DC bus voltage limit minus DC bus voltage) is used to increase an inverter output frequency until the voltage limit condition subsides, and, wherein during a current limit condition a current error signal (i.e. motor current limit minus motor current) is used to reduce inverter output frequency until the current limit condition subsides, a slew rate used to control the output frequency when neither a current nor a voltage limit condition exists, the slew rate decreased as a function of the voltage limit period durations and increases a function of the current limit period durations.


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