The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 2001

Filed:

Dec. 18, 1998
Applicant:
Inventors:

Janusz Bryzek, Fremont, CA (US);

David W. Burns, San Jose, CA (US);

Steven S. Nasiri, Saratoga, CA (US);

Sean S. Cahill, Palo Alto, CA (US);

Assignee:

Maxim Integrated Products, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/982 ; H01L 2/984 ; H01L 2/720 ;
U.S. Cl.
CPC ...
H01L 2/982 ; H01L 2/984 ; H01L 2/720 ;
Abstract

A semiconductor pressure sensor compatible with fluid and gaseous media applications is described. The semiconductor pressure sensor includes a sensor capsule having a semiconductor die and a silicon cap that is bonded to the semiconductor die. The semiconductor die includes a diaphragm that incorporates piezoresistive sensors thereon, and a stress isolation mechanism for isolating the diaphragm from packaging and mounting stresses. The silicon cap includes a cavity for allowing the diaphragm to deflect. The semiconductor pressure sensor further includes a pressure port that is hermetically attached to the semiconductor die. The sensor capsule and pressure port may be incorporated into a plastic housing. In one embodiment, the silicon cap is bonded to the semiconductor die to form an integral pressure reference. In an alternative embodiment, a second pressure port is provided for allowing gage or differential pressure measurements. A technique for incorporating the piezoresistive sensors is also described. An ASIC may be optionally attached to the silicon cap, and/or active electronic circuitry may be fabricated on the semiconductor die or silicon cap. Additional coatings may be optionally applied to the pressure port and semiconductor die for enhancing chemical resistance.


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