The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 2001
Filed:
Mar. 23, 1999
Takanori Ozawa, Kyoto, JP;
Rohm Co., Ltd., Kyoto, JP;
Abstract
In a ferroelectric memory and a method of manufacturing it, a metallic layer,of Ni, which is silicified at a temperature lower than the temperature when a ferroelectric layer FL looses ferroelectricity non-reversibly, is formed so as to be partially brought into contact with the upper surface of one of the source/drain regions,. Thereafter, the metallic layer,is; heated at the temperature lower than the temperature when the ferroelectric layer FL looses the ferroelectricity non-reversibly. Thus, the metallic layer,is silicified to form a silicide layer,. Therefore, without deteriorating the function of the ferroelectric layer FL, the portion of the metallic layer,which is contact with the upper surface of the source/drain region,can be sufficiently silicified. Ni has a very weak reduction/catalysis function for the ferroelectric layer FL. Therefore, the metallic layer,not silicified does not adversely affect the ferroelectric layer FL in the post manufacturing steps. Thus, the semiconductor device can give a small connection resistance between a silicon layer and a wiring layer while holding the function of a ferroelectric layer.