The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 2001
Filed:
Nov. 18, 1999
Applicant:
Inventor:
Frank M. Wanlass, Santa Clara, CA (US);
Assignee:
Other;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/18247 ;
U.S. Cl.
CPC ...
H01L 2/18247 ;
Abstract
This invention is a processing method for forming flash memory MOS transistors. The method uses chemical mechanical polishing to self align both a floating gate and an overlying control gate to the MOS channel region in both the width and length directions, thereby improving layout density. The method enables the capacitance between the control gate and the floating gate to be much larger than the capacitance between the floating gate and the channel; this reduces programing voltages. The method does not require any Shallow Trench Isolation (STI), and does not require Local Oxidation of Silicon (LOCOS), thereby resulting in little damage to the silicon.