The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 01, 2001
Filed:
Dec. 23, 1997
Milton Hiroki Sawasaki, Sao Paulo, BR;
Chantal Ykman-Couvreur, Brusell, BE;
Bill Lin, Leuven, BE;
Hugo De Man, Leuven, BE;
IMEC, Leuven, BE;
Abstract
A flip-flop-based circuit architecture generates a hazard-free asynchronous signal given the SET and RESET sum-of-product (SOP) solutions to an asynchronous process. The flip-flop SET and RESET SOP solutions can be hazardous. Thus, general purpose synchronous optimization tools (which are indifferent to hazards) can be used to derive the optimal SOP solutions. A fixed layer built around the SOP cores eliminates all hazards in the circuit. In one embodiment, the architecture is optimized by eliminating an RS latch and delay lines in the SOP cores. The architecture of the present invention is guaranteed to admit any semi-modular race-free state graph representation of an asynchronous process that satisfies the n-shot requirement. The state graph representations can be examined to determine if alternate, solution-specific, simplified architectures can be employed that further decrease the final area by the elimination of flip-flops or the elimination of a timing delay.