The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2001

Filed:

Dec. 14, 1998
Applicant:
Inventors:

Stephen C. Hilla, Raleigh, NC (US);

James M. Edwards, Cary, NC (US);

Timothy F. Masterson, Raleigh, NC (US);

William E. Jennings, Cary, NC (US);

Assignee:

Cisco Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
A03M 1/300 ;
U.S. Cl.
CPC ...
A03M 1/300 ;
Abstract

An error detection generator calculates error detection data for insertion into encapsulated frames. The error detection generator is configured to calculate multiple error detection values and insert them into corresponding fields of the encapsulated frames. The error detection generator includes a controller, three cyclic redundancy check (CRC) engines and at least one multiplexer. Each CRC engine is selectively enabled by the controller to calculate a frame check sequence (FCS) value on a different portion of the frame. Downstream CRC engines also receive the outputs from the upstream CRC engines so that these earlier FCS values may be used during subsequent calculations. The outputs of the CRC engines are also inserted into the appropriate fields of the encapsulated frames by the multiplexer.


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