The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2001

Filed:

Sep. 16, 1998
Applicant:
Inventor:

Cheol-ha Lee, Kyungki-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 2/900 ;
U.S. Cl.
CPC ...
G11C 2/900 ;
Abstract

Integrated circuit memory devices include a stress voltage generator that generates a stress voltage that is higher than the internal supply voltage of the integrated circuit memory device and that applies the stress voltage to the memory cell array during the stress BIST of the memory cell array. The stress voltage generator is preferably responsive to a BIST request signal and to a stress test signal that are applied from external of the integrated circuit memory device, to apply the stress voltage to the memory cell array and to perform a BIST of the memory cell array. The stress voltage generator is responsive to the BIST request signal and absence of the stress test signal, to apply the internal supply voltage to the memory cell array and to perform a BIST of the memory cell array. Accordingly, circuits within the integrated circuit memory device can be responsive to external test signals to generate stress voltages during BIST.


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