Bifurcated data and command/address communication bus architecture for random access memories employing synchronous communication protocols

Abstract

A computer memory device featuring a high-bandwidth memory interface to transfer information between a controller and the memory cells of a memory modules. Bifurcated communication buses is provided to take advantage of the interface. One of the bifurcated communication busses is dedicated to data information transfer, dataLink, between the controller and the memory modules, with the remaining bus, commandLink, being dedicated to command/address information transfer therebetween. This facilitates communication between the controller and the memory modules using information packets, bifurcated into data packets and command/address packets. To that end, the interface circuitry includes encoded chip select techniques that employs slaveId comparison logic, a plurality of control registers and delay registers to regulate the synchronization of communication transfers over the commandLink and the dataLink, as well as a queue register in which the packets are temporarily stored. The packets are scheduled to be placed on the appropriate busses so as to maximize data transfer, while minimizing power consumption of the memory device. Synchronization of the communication transfers on the commandLink and the dataLink is achieved during initialization of the memory device and may be periodically checked during normal operations, without degrading transfer throughput.