The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2001

Filed:

Dec. 06, 1999
Applicant:
Inventors:

Jun Nakai, Hyogo, JP;

Yutaka Ikeda, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/08 ; G11C 7/12 ;
U.S. Cl.
CPC ...
G11C 7/08 ; G11C 7/12 ;
Abstract

Only one sense signal line for driving a sense amplifier is arranged in each sense amplifier band. Each sub-array is provided with a sub-sense signal generator for generating two sub-sense signals in response to a main sense signal sent from one main sense signal line. The sub-sense signal is applied to the plurality of sense amplifiers corresponding to each sub-array. Since only one main sense signal line is arranged in each sense amplifier, a layout area is reduced. Preferably, a transistor of a first inverter in the sub-sense signal generator is smaller in size than a transistor of a final inverter. Thereby, a significant delay of the sub-sense signal does not occur in a position remote from a source of the main sense signal.


Find Patent Forward Citations

Nakai, Jun. (2001). Semiconductor memory device with hierarchical control signal lines (U.S. Patent No. 6226208). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6226208

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…