The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 01, 2001
Filed:
Sep. 01, 1999
Kouichi Ishimi, Tokyo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
When a reset signal (PLL-RST) is input, an arithmetic unit (,) measures the cycle of an input clock (IN) with a pulse counter (,) and based on the measured cycle, calculates a count value such that a delay clock (DL-OUT) and an input clock (IN) may come into synchronization with each other, to set it to a counter (,). The counter (,) thereafter changes the count value step by step in accordance with an output signal from a phase comparator (,). After the count value of the counter (,) is set by the arithmetic unit (,), an arithmetic unit (,) calculates a count value such that an output clock (PLL-OUT) and the input clock (IN) may come into synchronization with each other, to set it to a counter (,). The counter (,) changes the count value step by step in accordance with an output signal from a phase comparator (,) only when the two phases compared by the phase comparator (,) coincide with each other. With this configuration, a transition period to achieve a stable output clock can be reduced.