Integrated circuit buffers having reduced power consumption requirements

Abstract

Integrated circuit buffers include an inverter and a circuit that selectively powers the inverter at a first potential (e.g., V,−&agr;) when the output of the inverter is at a first logic level (e.g., logic 0) and at a second higher potential (e.g., V,) when the output of the inverter is at a second logic level (e.g., logic 1) opposite the first logic level. The integrated circuit buffer may include an inverter configured as a PMOS pull-up transistor having a gate electrode electrically coupled to an input node (IN) and a drain electrode electrically coupled to an output node (OUT), and an NMOS pull-down transistor having a gate electrode electrically coupled to the input node and a drain electrode electrically coupled to the output node. A diode and switch are also provided to perform the selective powering operation. The diode is provided to reduce the magnitude of the power supply signal the inverter receives when the PMOS pull-up transistor is inactive (thereby reducing the leakage current through the PMOS pull-up transistor) and the switch is provided to bypass the diode when PMOS pull-up transistor is active.