The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 01, 2001
Filed:
Mar. 03, 1998
Koji Fujii, Tokyo, JP;
Takakuni Douseki, Tokyo, JP;
Nippon Telegraph & Telephone Corporation, Tokyo, JP;
Abstract
A dynamic logic circuit comprising a plurality of unit dynamic logic circuits sequentially coupled in a multiple-stage fashion, each of which unit dynamic logic circuits including: a logic circuit portion formed by one or more than one MOS transistors; a first MOS transistor for a precharging or a pre-discharging operation with respect to the logic circuit; and a second MOS transistor to enable the logic circuit a discharging or a charging operation; wherein the MOS transistors composing the logic circuit portion are configured by low-threshold MOS transistors; and the second MOS transistor to enable the discharging or charging operation is composed of a high-threshold MOS transistor. The dynamic circuit is applied to a plural stage of combinational circuits in a self-timed pipelined datapath system, whereby a static leakage current at charging or pre-discharging operation can be reduced, resulting in decrease of power dissipation.