The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2001

Filed:

Oct. 29, 1999
Applicant:
Inventor:

Kamesh V. Gadepally, San Jose, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/701 ; H01L 2/712 ; H01L 3/10392 ;
U.S. Cl.
CPC ...
H01L 2/701 ; H01L 2/712 ; H01L 3/10392 ;
Abstract

A low stress active area silicon island structure with a reduced susceptibility to gate polysilicon layer “wraparound” and stringer formation during subsequent semiconductor manufacturing. The structure includes a semiconductor substrate (e.g. a silicon wafer) with an electrical insulation layer (e.g. a SiO,layer) thereon. The electrical insulation layer has an active area opening extending from its surface to the surface of the underlying semiconductor substrate. The structure also includes an active area silicon island filling the active area opening. A cross-section of the active area silicon island perpendicular to the surface of the semiconductor substrate has a non-rectangular profile, for example a “wineglass” profile. A process for the formation of a low stress active area silicon island structure includes first providing a semiconductor substrate, followed by forming an electrical insulation layer thereon. An active area opening with a non-rectangular cross-sectional profile is then created in the electrical insulation layer, extending from its upper surface to the semiconductor substrate. An active area silicon layer is subsequently deposited, using a selective epitaxial silicon deposition process, to fill the active area opening and cover the electrical insulation layer. Next, the active area silicon layer is removed from the electrical insulation layer, while leaving the active area silicon layer in the active area opening. The removal of the active area silicon layer from the electrical insulation layer results in the formation of a low stress active area silicon island in the active area opening.


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