The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 01, 2001
Filed:
Dec. 09, 1998
Akiyoshi Watanabe, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A gate insulating film is formed on the surface of active regions of a semiconductor substrate, and a first polysilicon film is deposited on the semiconductor substrate. Impurities are selectively doped into the first silicon film in an area where a capacitor is to be formed. A dielectric film is formed on the first silicon film. A second silicon film doped with impurities is formed on the dielectric film. The second silicon film and dielectric film are patterned so that the second silicon film and dielectric film are left in the area where the capacitor is to be formed, and not left in the area where MISFET are to be formed. A third silicon film is deposited on the whole surface of the substrate. A mask pattern covers the surface of the third silicon film in the area included by the patterned second silicon film as viewed along a direction normal to the substrate surface and in the area where a gate electrode of MISFET is to be formed, and the silicon films are selectively etched under the conditions that the dielectric film is not etched. A semiconductor device can be formed which has a low voltage dependency of a capacitor electrostatic capacitance and a small variation of electrostatic capacitances.