The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2001

Filed:

Mar. 18, 1998
Applicant:
Inventors:

Min-xian Zhang, Algonquin, IL (US);

Vernon L. Brown, Barrington, IL (US);

George E. White, Marrietta, GA (US);

Lola Conway, Elgin, IL (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G03F 7/40 ;
U.S. Cl.
CPC ...
G03F 7/40 ;
Abstract

A process for forming a resistor whose dimensions can be accurately determined by a photoimaging process, thereby yielding a resistor whose size and resistance value render the resistor a viable alternative to discrete chip resistors. The resistor is formed of a photoimageable resistive thick-film material that enables the dimensions of a resistor to be determined directly by photodefinition instead of conventional screen printing. Electrically-conductive terminations are provided that determine the electrical length of the resistor. The terminations may be formed prior to depositing the resistive layer, or after the resistive layer has been photoimaged and developed. If the latter approach is used, the terminations may be formed by depositing a photoimageable layer on the resistor, photoimaging and developing the photoimageable layer so as to form openings that expose regions of the resistor, and then plating, e.g., electrolessly plating, a conductive material on the exposed regions of the resistor to form terminations that overlie the resistor. Alternatively, by formulating the photoimageable layer to be plateable, a second photoimageable layer can be deposited on the plateable photoimageable layer prior to plating the conductive material, and then photoimaged and developed to form openings that expose regions of the plateable photoimageable layer that are adjacent the regions of the resistor exposed by the openings in the plateable photoimageable layer. Thereafter, the conductive material can be plated on the regions of the resistor and the plateable photoimageable layer exposed by the openings to yield terminations and connectors to the resistor.


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