The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 2001

Filed:

Apr. 09, 1998
Applicant:
Inventors:

Carol A. Fields, Los Gatos, CA (US);

Timothy A. Tripp, San Jose, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

A method and apparatus for analyzing performance and density of a source design module for a target programmable gate array. The source design module is converted to logic for a selected target programmable gate array. Performance and density of the converted logic are then estimated. If the estimated performance level does not achieve a target performance level, then problematic design elements are automatically or optionally converted to functionally equivalent programmable gate array design elements. The performance and density of the target programmable gate array is again estimated using the new design elements. In another mode of operation, design guidance is provided in converting the problematic design elements.


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