Digital delay locked loop for reducing power consumption of synchronous semiconductor memory device

Abstract

A digital delay locked loop for a synchronous semiconductor memory device reduces power consumption by disabling the stages of the delay locked loop that are not required for generating an internal clock signal that is synchronized with an external system clock signal. The delay locked loop includes a first synchronous delay line formed from a plurality of serially connected unit delayers, a second synchronous delay line formed from a second plurality of serially connected unit delayers, a plurality of phase detectors arranged in successive order to compare the external clock signal to the plurality of delayed clock signals and generate a plurality of enable signals, and a plurality of switches arranged in successive order to select a delayed clock signal from the second delay line as an internal clock signal. Each stage includes one of the unit delayers in the first delay line, one of the unit delayers in the second delay line, one of the phase detectors, and one of the switches. Each of the phase detectors generates a carry signal if the clock signal from its stage is synchronized with the system clock or if it is downstream from the stage that is synchronized. The carry signal from each stage is coupled to the next successive stage. Each of the stages has one or more operation cutting circuits to disable the stage responsive to an active carry signal from the previous stage. The operation cutting circuits can be included in the phase detectors and the unit delayers in each stage to disable inverters in the unit delayers and latches in the phase detectors to conserve power in stages that are not necessary for generating the internal clock signal.