Integrated circuit memory devices having improved sense and restore operation reliability

Abstract

Integrated circuit memory devices include a control circuit that generates an active first control pulse (e.g., PR) having a first duration, in response to an active strobe pulse (e.g., /RAS) that may be generated during a data reading operation. To improve the reliability of the data reading operation and any subsequent data restore operation, particularly when the duration of the active strobe pulse is relatively short, a pulse width extension circuit is provided. The pulse width extension circuit converts the active first control pulse into an active second control pulse (e.g., PAIVCE,) having a second duration greater than the first duration. This active second control pulse is then provided as a control input to an internal voltage generator. The internal voltage generator is provided to drive a first supply signal line (e.g., AIVC,) at a first supply voltage in response to the active second control pulse. The first supply signal line may be provided as an internal supply line to one or more active circuits within the memory device. The first supply signal line may power a differential sense amplifier during data reading and data restore operations (i.e., when data is being sensed and amplified on a pair of differential bit lines). These reading and restore operations may be performed with higher reliability if the additional pulse duration provided by the pulse width extension circuit is sufficient to enable a complete recharging of the differential bit lines of the sense amplifier while a data restore operation is being performed.